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DATA SHEET
TDA8960 ATSC 8-VSB demodulator and decoder
Preliminary specification File under Integrated Circuits, IC02 1999 Jun 14
Philips Semiconductors
Preliminary specification
ATSC 8-VSB demodulator and decoder
FEATURES General features * One-chip Advanced Television Systems Committee (ATSC)-compliant demodulator and concatenated trellis (Viterbi)/Reed Solomon decoder with de-interleaver and de-randomizer * 0.4 m process * 3.3 V device * 64-lead QFP64 package * Boundary scan test * Output format: 8-bit wide bus. DOCUMENT REFERENCES 8-VSB demodulator * On-chip digital circuitry for tuner Automatic Gain Control (AGC) * Square root raised cosine filter with 11.5% roll-off factor * Fully internal carrier recovery loop * Mostly internal clock recovery and AGC loops with programmable loop filters * External indication of demodulator lock. Adaptive equalizer * Feed forward including a Decision Feedback Equalizer (DFE) structure * Range of -2.3 to +10.5 s * Adaptation based on ATSC field sync (trained) and/or 8-VSB data (blind) * Trellis (Viterbi) decoder * Rate 23 (Rate 12 Ungerboeck code based). Reed Solomon decoder * (207, 187 and T = 10) Reed Solomon code * Internal convolutional de-interleaving (I = 52; using internal memory) * External indication of uncorrectable error; transport error indicator bit in Motion Picture Export Group (MPEG) packet header is also set * Followed by de-randomizer based on ATSC standard. ORDERING INFORMATION TYPE NUMBER TDA8960 1999 Jun 14 PACKAGE NAME QFP64 DESCRIPTION
TDA8960
I2C-bus interface * I2C-bus interface to initialize and monitor the demodulator and Forward Error Correction (FEC) decoder. Operation without I2C-bus control is possible (default).
See the ATSC URL on `http://www.atsc.com' for the following related documents: * "ATSC Digital Television Standard" (document no. A/53, issued 1995 Sep 16) * "Guide to the use of the ATSC Digital Television Standard" (document no. A/54, issued 1995 Oct 04). APPLICATIONS * Digital ATSC compliant TV receivers * Personal computers with digital television capabilities * Set-top boxes.
VERSION
plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm SOT319-2 2
Philips Semiconductors
Preliminary specification
ATSC 8-VSB demodulator and decoder
GENERAL DESCRIPTION The TDA8960 is an ATSC-compliant demodulator and forward error correction decoder for reception of 8-VSB modulated signals for terrestrial and cable applications: * Terrestrial: reception of 8-VSB modulated signals via standard 6 MHz VHF/UHF terrestrial TV channels (TV channels 2 to 69 in the United States) * Cable: reception of 8-VSB modulated signals via standard 6 MHz VHF/UHF cable TV channels. Most of the loop components needed to recover the data from the received symbols are internal. The only required external loop components are a low-speed serial D/A converter and a Voltage Controlled crystal Oscillator (VCXO) for the symbol timing recovery and an opamp integrator for the AGC. Loop parameters of the clock and carrier recovery can be controlled by the I2C-bus. A tuner converts the incoming RF frequency to a fixed IF frequency centred at 44 MHz. The output of the tuner is filtered, followed by a down conversion in an IF block to a low IF frequency centred at 12 the VSB symbol rate (or a frequency of approximately 5.38 MHz). The low IF signal is applied to the A/D converter. To use its full input span, the A/D converter is located within what is typically a fine AGC loop which includes a variable gain stage at the output of the IF block. However, it is also possible to apply the TDA8960 AGC control output directly to the tuner. The detector for the TDA8960 AGC output is located after the A/D converter and determines the peak level of the incoming signals. After gain control, the low IF signal is sampled at a nominal rate of twice the VSB symbol frequency, or approximately 21.5 MHz.
TDA8960
The carrier recovery is performed completely internally. This function consists of a digital frequency and Frequency Phase-Locked Loop (FPLL). Data shaping is performed with a square root raised cosine (half Nyquist) filter with roll-off factor of 11.5%. Symbol timing recovery is performed mostly within the TDA8960, except that a low cost D/A converter and VCXO are required externally to generate the nominal 21.52 MHz clock signal for the A/D converter and TDA8960. After carrier recovery, half Nyquist filtering and symbol timing recovery, adaptive equalization is performed based on the use of the ATSC field sync (trained equalization) and/or the 8-VSB data itself (blind equalization). The adaptive equalizer uses a DFE structure. After trellis decoding, the stream is de-interleaved with a convolutional de-interleaver (interleaving depth 52). The memory for de-interleaving is on-chip. The Reed Solomon decoder is ATSC-compliant with a length of 207 and can correct up to 10 bytes. The decoded stream is de-randomized using a Pseudo Random Bit Sequence (PRBS). Finally the data is passed to a First-In, First-Out (FIFO) register that prevents the appearance of irregular gaps in the output data. The output of the TDA8960 is an ATSC-compliant MPEG-2 packet stream together with a clock. Furthermore some signal flags are provided to indicate the sync bytes and the valid data bytes. Uncorrected blocks are also indicated. The 8-bit wide MPEG-2 stream can be applied to an MPEG-2 transport demultiplexer.
1999 Jun 14
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Philips Semiconductors
Preliminary specification
ATSC 8-VSB demodulator and decoder
QUICK REFERENCE DATA SYMBOL VDDD IDDD(tot) fclk fsym IL ro tacq Tamb Ptot Note 1. This corresponds to 12 training sequences. PARAMETER digital supply voltage total digital supply current clock frequency symbol frequency implementation loss half Nyquist filter roll-off factor acquisition time ambient temperature total power dissipation note 1 VDDD = 3.3 V CONDITIONS 3.0 - - - - - - -20 - MIN. 3.3 300 21.52 10.76 - 11.5 - - 1.0 TYP. 3.6 - - - - - 290 +70 - MAX.
TDA8960
UNIT V mA MHz Msymbols/s dB % ms C W
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Philips Semiconductors
Preliminary specification
ATSC 8-VSB demodulator and decoder
BLOCK DIAGRAM
TDA8960
handbook, full pagewidth
EQLOCKINDIC LOCKINDIC 53 54 AGCOUT 56 ADIN0 to ADIN9 1 to 8, 11, 12 RESET LOCK DETECTORS DIGITAL FRONT-END(1) SERIAL DAC INTERFACE 61 62 63 64 TRSDO TRSTB TRCS TRLD 27 RSTAN
TRELLIS DECODER
TDA8960
17 DE-INTERLEAVER SYNCHRONIZATION REED SOLOMON DECODER BOUNDARY SCAN TEST 21 20 18 19
TDI TDO TRST TMS TCK
DE-RANDOMIZER I2C-BUS INTERFACE FIFO 23, 34, 45, 57, 9, 26, 41, 60
13 16 14 15 30, 38, 49,55, 10, 28, 42, 58
A0 A1 SCL SDA
59 CLK
29 DATACLK
31 to 33 35 to 37 39, 40
22
24
25
ERROR SOP DATAVALID
DATA7 to DATA0
VSSD1 to VSSD8 VDDD1 to VDDD8
MGR598
(1) The digital front-end consists of the following circuits: - Fine AGC - Carrier recovery - Half Nyquist filter
- Symbol timing recovery - Sync recovery and pilot removal - Adaptive equalization.
Fig.1 Block diagram.
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Philips Semiconductors
Preliminary specification
ATSC 8-VSB demodulator and decoder
PINNING SYMBOL ADIN0 ADIN1 ADIN2 ADIN3 ADIN4 ADIN5 ADIN6 ADIN7 VDDD5 VSSD5 ADIN8 ADIN9 A0 SCL SDA A1 TDI TMS TCK TRST TDO ERROR VDDD1 SOP DATAVALID VDDD6 RSTAN VSSD6 DATACLK VSSD1 DATA7 DATA6 DATA5 VDDD2 DATA4 DATA3 DATA2 VSSD2 DATA1 DATA0 1999 Jun 14 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 I/O I I I I I I I I - - I I I I I/O I I I I I O O - O O - I - O - O O O - O O O - O O DESCRIPTION data input bit 0 from ADC data input bit 1 from ADC data input bit 2 from ADC data input bit 3 from ADC data input bit 4 from ADC data input bit 5 from ADC data input bit 6 from ADC data input bit 7 from ADC digital supply voltage 5 (3.3 V) digital core ground 5 data input bit 8 from ADC data input bit 9 from ADC I2C-bus slave address bit 0 I2C-bus clock I2C-bus serial data I2C-bus slave address bit 1 TAP controller data input; note 1 TAP controller test mode select; note 1 TAP controller test clock; note 1 TAP controller asynchronous reset; note 1
TDA8960
TAP controller test data output (3-state); note 1 transport packet block error signal digital supply voltage 1 (3.3 V) start of transport packet signal transport packet data valid signal digital supply voltage 6 (3.3 V) asynchronous reset digital ground 6 transport interface data clock digital ground 1 transport packet data output bit 7 transport packet data output bit 6 transport packet data output bit 5 digital supply voltage 2 (3.3 V) transport packet data output bit 4 transport packet data output bit 3 transport packet data output bit 2 digital ground 2 transport packet data output bit 1 transport packet data output bit 0 6
Philips Semiconductors
Preliminary specification
ATSC 8-VSB demodulator and decoder
TDA8960
SYMBOL VDDD7 VSSD7 n.c. n.c. VDDD3 n.c. n.c. n.c. VSSD3 n.c. n.c. n.c. LOCKINDIC EQLOCKINDIC VSSD4 AGCOUT VDDD4 VSSD8 CLK VDDD8 TRSDO TRSTB TRCS TRLD Note
PIN 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
I/O - - digital ground 7 not connected not connected -
DESCRIPTION digital supply voltage 7 (3.3 V)
digital supply voltage 3 (3.3 V) not connected not connected not connected
-
digital ground 3 not connected not connected not connected
O O - O - - I - O O O O
lock indicator of front-end lock indicator of equalizer digital ground 4 AGC control signal (3-state) digital supply voltage 4 (3.3 V) digital ground 8 clock digital supply voltage 8 (3.3 V) serial data to DAC strobe signal to DAC chip select signal to DAC load signal to DAC
1. In accordance with the "IEEE 1149.1" standard; pads TCK, TDI, TMS and TRST are input pads with an internal pull-up transistor and pad TDO is a 3-state output pad.
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Philips Semiconductors
Preliminary specification
ATSC 8-VSB demodulator and decoder
TDA8960
54 EQLOCKINDIC
handbook, full pagewidth
53 LOCKINDIC
56 AGCOUT
61 TRSDO
57 VDDD4
60 VDDD8
55 VSSD4
58 VSSD8
62 TRSTB
63 TRCS
64 TRLD
59 CLK
52 n.c. 51 n.c. 50 n.c. 49 VSSD3 48 n.c. 47 n.c. 46 n.c. 45 VDDD3 44 n.c. 43 n.c. 42 VSSD7 41 VDDD7 40 DATA0 39 DATA1 38 VSSD2 37 DATA2 36 DATA3 35 DATA4 34 VDDD2 33 DATA5 DATA6 32
ADIN0 ADIN1 ADIN2 ADIN3 ADIN4 ADIN5 ADIN6 ADIN7 VDDD5
1 2 3 4 5 6 7 8 9
VSSD5 10 ADIN8 11 ADIN9 12 A0 13 SCL 14 SDA 15 A1 16 TDI 17 TMS 18 TCK 19 TRST 20 TDO 21 ERROR 22 VDDD1 23 SOP 24
TDA8960
DATAVALID 25
VDDD6 26
RSTAN 27
VSSD6 28
DATACLK 29
VSSD1 30
DATA7 31
MGR599
Fig.2 Pin configuration.
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Philips Semiconductors
Preliminary specification
ATSC 8-VSB demodulator and decoder
FUNCTIONAL DESCRIPTION The internal architecture of the TDA8960 consists of basically two parts: * The front-end containing the AGC, carrier recovery, half Nyquist filter, symbol timing recovery, sync recovery and adaptive equalization * The back-end containing the trellis decoder, de-interleaver, the Reed Solomon decoder and de-randomizer.
handbook, halfpage
TDA8960
By default the carrier is present at 2.69 MHz. During carrier recovery a shift is applied such that the pilot is present at DC. It can happen that the pilot is present at the higher edge of the VSB spectrum. In this event the CR_INV bit in I2C-bus register 08H (see Table 13) can be set to make sure that after the shift the pilot is at DC.
MGR600
AGC This block controls an analog gain over a range of up to 20 dB. The data from the A/D converter (Philips Semiconductors' TDA8763 is recommended) arrives at the VSB demodulator via inputs ADIN9 to ADIN0, which is10-bit wide. The format of the incoming samples can be programmed using the I2C-bus accessible register 08H. By writing to bit 3 the format can be either twos complement or binary. The absolute value of the input signal is averaged over several samples. The filtered signal is compared to a threshold. The threshold consist of a 4-bit signed value which can be programmed using the I2C-bus. The 3-state output signal charges or discharges an off-chip ideal integrator and is used to control the gain controller of the tuner front-end module. The values of the signal are shown in Table 1. Table 1 AGC output COMMENT output of the filter is smaller than the threshold output of the filter is larger than the threshold output of the filter is equal to the threshold
amplitude (dB)
5.38 MHz
2.69
5.38
8.07 frequency (MHz)
Fig.3 Signal spectrum during carrier recovery.
The carrier recovery is capable of tracking a frequency offset of up to 100 kHz from the nominal frequency offset within 100 ms. By means of I2C-bus read register 03H the current frequency offset in the carrier recovery can be read. This value can be used for fine tuning applications. Sync recovery and pilot removal This block performs several functions including pilot removal, segment and field sync removal and rescale AGC based on the segment sync. If this block is able to find a data segment sync signal, the external pin LOCKINDIC is asserted. The value of this signal can also be read through I2C-bus control. Adaptive equalization The equalizer consists of a forward filter and a feedback filter section. Demodulated symbols from the synchronization and pilot removal block are received every symbol period. The equalizer tries to invert the effects of the channel on the transmitted symbol stream by filtering these symbols. The coefficients of the filters are updated every symbol period using the training sequence. There is also a provision to perform blind equalization. The filtered output is available for the next block, the trellis decoder.
PIN AGCOUT 1 0 Z
The analog low-pass filter or integrator circuit should be designed with an 8 ms time constant. The response of the gain amplifier is linear with respect to the control voltage over the desired range of operation. Carrier recovery This circuit recovers the frequency and phase of the pilot carrier. The spectrum during the carrier recovery is displayed in Fig.3. 1999 Jun 14 9
Philips Semiconductors
Preliminary specification
ATSC 8-VSB demodulator and decoder
The equalizer has been designed to correct a maximum pre-echo of 2.32 s and a maximum post-echo of 10.50 s. The equalizer uses an overlapping DFE to reduce the effects of co-channel interference. The equalizer has been optimized to have a typical acquisition time of 12 training sequences, which corresponds to approximately 290 ms. The acquisition time has been defined as the time when the output signal-to-noise ratio reaches the Threshold Of Visibility (TOV). The ATSC defines a TOV of 14.9 dB for 8-VSB. Based on the training signal and the output of the equalizer the Mean Square Error (MSE) signal is generated. This 16-bit value is used to control the channel adaptation process and is available though I2C-bus control. Control The TDA8960 contains a complicated finite state machine. This state machine controls the sequence of operations that must be performed when a valid VSB data signal is detected in order for it to be properly decoded into a stream of MPEG-2 transport packets. The following steps have to take place: 1. The external tuner is directed to lock to a specified channel frequency. A VSB signal is present. 2. The tuner AGC locks to an acceptable signal gain. 3. The coarse AGC of the TDA8960 locks to acceptable A/D converter gain. 4. The timing and carrier recovery loops lock to the symbol clock and the carrier frequency. 5. The segment sync pattern is detected. The segment sync lock is acquired. 6. The fine AGC locks. 7. The field sync pattern is detected. The MSE of the received field sync training sequence is determined. 8. The equalizer uses subsequent training sequences to adapt itself to the channel conditions. 9. The equalizer adapts to the point that the MSE of the training sequence is sufficiently small. The trellis decoding, convolutional de-interleaving and Reed Solomon decoding processes all begin. 10. Valid MPEG-2 transport packets are generated. The finite state machine consists of three states. After a reset has been applied, the state machine starts in state 0. STATE 0: CHANNEL ACQUISITION
TDA8960
In this state either no channel signal is present or a channel signal is being acquired. The AGC, timing recovery and carrier recovery loops must first lock onto it. If the segment sync lock is lost, pin LOCKINDIC is LOW, or a hardware reset is applied to the VSB demodulator, the finite state machine returns to state 0. STATE 1: EQUALIZER TRAINING The finite state machine remains in state 1 until the MSE of the equalized training sequence falls below a certain threshold. It should be noted that in state 1 the back-end is continuously reset to make sure that after the demodulator has locked onto a signal, the trellis decoder and following processing blocks begin at the start of the next complete data field. By means of I2C-bus registers 01H and 02H the MSE value of the equalizer can be read. This value can be used for applications such as antenna pointing. STATE 2: NORMAL OPERATION Normally the state machine would remain in state 2 as long as no synchronization error occurs. If the MSE of the equalized training sequence is exceeded for more than 100 ms, the equalizer is reset for one symbol period and the adaptation process starts again. If the demodulator is in this state, the EQLOCKINDIC pin signal goes up. The value of this signal can also be read through the I2C-bus.
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Philips Semiconductors
Preliminary specification
ATSC 8-VSB demodulator and decoder
DAC interface
TDA8960
The TDA8960 D/A interface connects to an external off-chip serial D/A converter. It supports four different serial modes. EXTERNAL INTERFACE The DAC interface consists of pins 61 to 64; see Table 2. Table 2 DAC interface PIN TRSDO TRSTB TRCS TRLD OUTPUT MODES Table 3 shows which DACs can be used in the different output modes. Table 3 DAC serial interface modes and DAC types POLARITY +dF/dV SET-UP TIME (ns) 67 EXAMPLE DEVICE Maxim MAX531, MAX538, MAX539, MAX504 and MAX515 Texas Instruments TLC5615 Sipex SP9500 and SP960 Linear Technology TLC1451 1 2 3 +dF/dV +dF/dV -dF/dV 45 45 67 Analog Devices AD7943 Analog Devices DAC8512 same types as mode 0 serial data output strobe signal which can be used by the DAC to shift in serial data chip select signal for DAC is also used by some DACs to load serially shifted data in the internal parallel register on the positive edge load signal used by some DACs to load serially shifted data in the internal parallel latches FUNCTION
OUTPUT MODE 0
The operating mode is programmed by means of the I2C-bus interface. Bits 4 and 5 of registers 09H control the mode; see Table 13. The timing diagrams of the different serial modes are shown in Fig.4. Modes 0 and 3 do not use the load signal available at pin TRLD. In mode 3 the output of the timing recovery low-pass filter is inverted to control VCXOs which have a negative dF/dV. Modes 0 and 3 can provide up to 67 ns of the serial data set-up time from the moment the TRSDO output has a new data bit until the start of the TRSTB pulse. In mode 1 the TRCS pin is not used.
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Philips Semiconductors
Preliminary specification
ATSC 8-VSB demodulator and decoder
TDA8960
handbook, full TRCS pagewidth
TRSTB
TRSDO
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
MGR601
a. Modes 0 and 3
handbook, full pagewidth TRSTB
TRSDO
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
TRLD
MGR602
b. Mode 1
handbook, fullTRCS pagewidth
TRSTB
TRSDO
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
TRLD
MGR603
c. Mode 2
Fig.4 Timing diagrams of the different DAC serial interface modes.
1999 Jun 14
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Philips Semiconductors
Preliminary specification
ATSC 8-VSB demodulator and decoder
Transport stream interface The transport stream interface provides an output of 8-bit parallel MPEG-2 transport packets at a data rate of 5.38 Mbytes/s. IMPLEMENTATION The transport interface consists of a FIFO, which has two tasks: 1. Removal of the field sync segment from the generation of output data 2. Increase of the data rate of the de-randomizer from 2.69 to 5.38 MHz.
TDA8960
Basically the 208 bytes of a field segment (187 data bytes, 20 error correcting bytes and one segment sync byte) are distributed over the remaining 312 data segments. The FIFO has a depth of two data segments. As the output data rate is 5.38 MHz we have to distribute 416 bytes, or two field sync data segments over 312 data segments. Every MPEG-2 transport packet corresponding to a data segment gets a delay equal to one 5.38 MHz clock cycle. Further, every third MPEG-2 transport packet gets an extra delay of one 5.38 MHz transport packet. EXTERNAL INTERFACE The transport stream consists of four signals and one data bus as shown in Table 4.
Table 4
Transport stream interface NAME FUNCTION output clock valid demodulator output data or one valid MPEG transport packet output data stream (8-bit wide output bus) indicates the start of a packet. It goes HIGH at the start of a packet and remains HIGH during the first byte of the packet, the so called sync byte a transport packet error indicator, which is HIGH for each 188 byte transport packet in which the Reed Solomon decoder found more errors than it could correct
DATACLK DATAVALID DATA[7 to 0] SOP ERROR
FUNCTIONAL DESCRIPTION The timing of the transport stream interface signals is shown in Fig.5.
handbook, full pagewidth
185.9 ns
DATACLK 77.5 s DATAVALID 188 bytes/34.9 s DATA7 to DATA0 00H
MPEG-2 sync byte
00H
sync
185.9 ns SOP 188 bytes/34.9 s ERROR
MGR604
Fig.5 Timing diagram of the transport interface (normal mode).
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Philips Semiconductors
Preliminary specification
ATSC 8-VSB demodulator and decoder
The DATACLK signal is the 5.38 MHz demodulator output clock. It is derived from the system clock of 21.52 MHz. A few remarks can be made about the DATACLK signal: * If a reset is applied, DATACLK becomes LOW; it remains LOW until reset is released and the symbol timing recovery block has detected the synchronization signals * After a channel change the DATACLK signal stops; it starts again after the system has been locked on to a valid signal * If the Reed Solomon decoder produces an invalid transport packet and the ERROR signal is asserted the DATACLK signal continues to change state * If the sync recovery block is not able to detect the field sync or data segment sync, DATACLK will not change. The DATAVALID signal indicates valid demodulator output data or one valid MPEG-2 transport packet. It is active HIGH for 188 bytes, or 34.9 s. The zero bytes to be sent after the 188 valid bytes of the transport packet can be considered to be zeroed parity bytes. SOP or start of packet signal is HIGH during the first byte of the packet. The ERROR signal indicates that the transport packet contains uncorrectable output. The ERROR signal becomes HIGH in the following situations:
TDA8960
* If the Reed Solomon decoder is unable to correct all errors in a transport packet * After a reset has been applied, the ERROR signal is asserted; it remains HIGH until a valid transport packet is produced by the demodulator * If the demodulator is out of sync, thus can not detect the field sync and segment sync in the incoming data stream. The ERROR signal can be asserted in the middle of a transport packet.
Sync byte and transport error indicator
The structure of a transport packet header is shown in Fig.6. For the VSB demodulator only the first two bytes of the so called transport packet header are important. The first byte in each header of a transport packet is the so called MPEG-2 packet synchronization byte (sync byte). As specified in the MPEG-2 standard, this sync byte must have the same value for all packets. The VSB demodulator IC sets this byte for each outgoing transport packet to 47H. The MSB of the second byte in the transport packet is the transport_error_indicator bit. It indicates that the Reed Solomon decoder was not able to correct all errors and the transport packet has invalid data.
handbook, full pagewidth
188 bytes adaptation field (if present) payload (if present)
transport packet header 0 1 0 0 0 1 1 1 1st byte
sync byte 4th byte MSB transport_error_indicator LSB
MGR605
Fig.6 The structure of a transport packet header.
1999 Jun 14
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Philips Semiconductors
Preliminary specification
ATSC 8-VSB demodulator and decoder
Boundary scan interface The TDA8960 Test Access Port (TAP) conforms to the "IEEE 1149.1 Joint Test Action Group (JTAG)" standard. It is used for board level testing of integrated circuits and for testing the internals of an integrated circuit. The JTAG standard defines on-chip test logic, which consists of an instruction register, a group of test data registers including Table 5 Public instruction codes INSTRUCTION BYPASS(1) SAMPLE(2) EXTEST(3) INTEST(4) IDCODE(5) Notes CODE 1111 0001 0000 0011 0010
TDA8960
a bypass register and a boundary scan register, four dedicated pins collectively called the Test Access Port (TAP) and a TAP controller. INSTRUCTION REGISTER The instruction register consists of four bits without parity. There are five defined public instructions; see Table 5.
SELECTED DATA REGISTER bypass (initialized state) boundary scan boundary scan boundary scan identification or bypass
1. The bypass instruction provides a minimum length (1-bit) serial path between the TDI and TDO pins when no test operation is required. 2. This instruction can be used to take a sample of the inputs and outputs during normal operation of the component. It can also be used to preload data values into the latched outputs of the boundary scan register. 3. This instructions allows testing off-chip circuitry and board level interconnections. 4. This instruction allows low speed, static testing of the on-chip logic. It can also be used after the chip is mounted on a printed circuit board. 5. This instruction will return the manufacturer ID, part number code and version code. For the TDA8960 the manufacturer ID is `B00000010101', the part number code is `SVSB' and the version code is `D1'. In addition three private instructions are implemented to control different test modes; see Table 6. Table 6 Private instruction codes INSTRUCTION SCAN_TEST BIST_TEST RAM_TEST CHAR_MODE CODE 1000 1001 1010 1011 TEST MODE test on-chip scan chains BIST test of de-interleaver RAM scan test of the on-chip memories characterization mode
In the characterization mode the IC is scan-testable in the same way as in the scan test mode. However the outputs are not switched to the scan chain outputs. The outputs retain their functionality. It is now possible to scan test pattern through the logic and to verify if the timing constrains at the outputs are met.
EXTERNAL INTERFACE The TAP consists of five pins as shown in Table 7.
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Philips Semiconductors
Preliminary specification
ATSC 8-VSB demodulator and decoder
Table 7 TAP external interface SIGNAL TMS TCK TDI TDO TRST OPERATION The TAP controller is a finite state machine. It selects a JTAG instruction or a data register to store the input based on the TMS signal, receives instructions and data on the TDI pin, executes the instruction when triggered by TMS, and shifts data out of TDO. TCK provides the clock signal for the test logic required by the standard. TCK is asynchronous to the system clock. Stored devices in the JTAG controller must retain their state indefinitely when TCK is stopped at logic 0. The signal received at TMS is decoded by the TAP controller to control test functions. The logic is required to sample TMS at the rising edge of TCK. Serial test instructions and test data are received at TDI. The TDI signal is required to be sampled at the rising edge of TCK. When test data is shifted from TDI to TDO, the data must appear without inversion at TDO after a number of rising and falling edges of TCK, determined by the length of the instruction or test data register selected. TDO is the serial output for test instructions and data from the TAP controller. Changes in the state of TDO must occur after the falling edge of TCK. This is because devices connected to TDO are required to sample TDO at the rising edge of TCK. The TDO driver must be in an inactive state (i.e. TDO line must be flat) except when the scanning of data is in progress. I2C-bus interface The I2C-bus interface is used to write control information to and read low-speed diagnostic information from the TDA8960. The key features of the I2C-bus interface are: * I2C-bus data rate up to 400 kbits/s * Support for only 7-bit addressing and the possibility of modifying the slave address externally. A typical system using the I2C-bus interface is illustrated in Fig.7. The TDA8960 is connected as a slave to a master through SCL and SDA. Note that the bus has one pull-up resistor for each of the clock and data lines. 1999 Jun 14 16 TYPE I I I O I test clock test data input test data output
TDA8960
DESCRIPTION test mode select
test asynchronous reset
handbook, halfpage
VDD
I2C-BUS MASTER
TDA8960
Rpu
Rpu
SCL SDA
MGR606
Fig.7 Typical I2C-bus system implementation.
EXTERNAL INTERFACE The I2C-bus interface consists of four signals as shown in Table 8. Table 8 I2C-bus external interface TYPE I/O I I I I2C-bus I2C-bus I2C-bus DESCRIPTION serial data clock slave address bit 0
SIGNAL SDA SCL A0 A1
I2C-bus slave address bit 1
The TDA8960 has 3.3 V I/O and I2C-bus pins. Therefore, in a complete system some circuitry might be necessary to allow ICs with different supply voltages to communicate and be controlled. This has been described in an application report available from Philips Semiconductors (application report "AN97055", issued 1997 Aug 04).
Philips Semiconductors
Preliminary specification
ATSC 8-VSB demodulator and decoder
ADDRESSING THE DEVICE Addressing the VSB demodulator over the system the I2C-bus requires that the 7-bit slave address (A6 to A0) of the device is sent over the bus in accordance with the protocols, together with the R/W bit equal to logic 1 or 0 to write or read data respectively. Table 9 A6 0 Slave address A5 0 A4 0 A3 1 A2 1 A1 A1 A0 A0
TDA8960
The slave address of the device is shown in Table 9. Bits 0 to 6 are predefined, but bits 0 and 1 can be set using the external pins A0 and A1.
R/W 0 = write 1 = read
handbook, full pagewidth
(1)(2)
(1)
(1)(3)
(4)(5)
(1)
(4)(5)
(1) (4)(5)(6)
(1)(7)
S
SLAVE ADDRESS
R/W
A
DATA
A
DATA
A/A
P
(8)
MGR607
(1) (2) (3) (4)
From master to slave S = START condition Logic 0 (write) From slave to master
(5) (6) (7) (8)
A = acknowledge (SDA LOW) A = not acknowledge (SDA HIGH) P = STOP condition Data transferred (n bytes + acknowledge).
Fig.8 A master-transmitter addresses a slave receiver with a 7-bit address (write access).
A write operation is shown in Fig.8. After the START condition, the slave address followed by the R/W bit is transmitted. The receiver, the TDA8960, sends an acknowledge and the transmitter starts sending the register values. After each received byte, the TDA8960 sends an acknowledge. The transfer stops if the TDA8960 does not acknowledge the transfer and/or the master sends a STOP condition. If register 08H has to be written to, eight consecutive bytes are written. The first corresponds to register 01H, the second to 02H and so on. The TDA8960 will auto-increment the accessed address automatically. Up to ten consecutive addresses can be written.
In Table 11 the default values are given for a number of reserved addresses and reserved bits of certain addresses. These correct default values have to be written in order to prevent unexpected behaviour of the IC. Figure 9 shows a read operation. The master sends a START condition followed by the slave address and the R/W bit is set to logic 1. The slave returns an acknowledge followed by the value of the first address. The master sends another acknowledge and the next value of the address is returned. If the master transmits a STOP condition after the acknowledge, the transfer is stopped. Up to three consecutive addressed (00H to 03H) can be read.
1999 Jun 14
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Philips Semiconductors
Preliminary specification
ATSC 8-VSB demodulator and decoder
TDA8960
handbook, full pagewidth
(1)(2)
(1)
(1)(3)
(4)(5)
(4)
(1)(5)
(4)
(1)(6)
(1)(7)
S
SLAVE ADDRESS
R/W
A
DATA
A
DATA
A
P
(8)
MGR608
(1) (2) (3) (4)
From master to slave. S = START condition. Logic 1 (read). From slave to master.
(5) (6) (7) (8)
A = acknowledge (SDA LOW). A = not acknowledge (SDA HIGH). P = STOP condition. Data transferred (n bytes + acknowledge).
Fig.9 A master-transmitter addresses a slave receiver with a 7-bit address (read access).
Table 10 I2C-bus control register overview (write); note 1 FUNCTION Operation Reserved Reserved Operation Reserved Reserved Reserved Reserved Carrier recovery Timing recovery Note 1. Do not write past address 09H. Table 11 I2C-bus control registers (default settings after reset) FUNCTION Operation Reserved Reserved Operation Reserved Reserved Reserved Reserved Carrier recovery Timing recovery ADDRESS 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H D7 0 0 0 0 0 1 0 1 0 0 D6 0 0 0 0 0 0 0 1 0 0 D5 0 0 0 0 0 0 0 0 0 0 D4 0 0 0 0 0 0 0 0 0 0 D3 0 0 0 0 0 0 0 1 0 0 D2 0 0 1 0 0 0 0 0 1 0 D1 0 0 0 0 1 0 0 1 0 0 D0 0 0 0 0 0 0 0 0 0 0 ADDRESS 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H INTMOD AD_FMT CR_INV AGC_THRES D7 D6 D5 D4 D3 D2 D1 GNRL_RST D0 INITIAL_RST
1999 Jun 14
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Philips Semiconductors
Preliminary specification
ATSC 8-VSB demodulator and decoder
Table 12 I2C-bus diagnostic registers overview (read); note 1 FUNCTION Operation Equalizer Carrier recovery Note 1. Do not read past address 03H. Table 13 I2C-bus control registers (write); notes 1 and 2 ADDRESS 00H FUNCTION operation COMMENTS reserved general reset (note 1) initial reset (note 2) 03H operation reserved AGC threshold value 08H carrier recovery reserved A/D input format inverted spectrum reserved 09H timing recovery reserved DAC interface mode BIT 7 to 2 1 0 7 to 4 3 to 0 AGC_THRES 7 to 4 3 2 1 to 0 7 to 6 5 to 4 INT_MOD AD_FMT CR_INV 0 = twos complement 1 = binary 0 = pilot at 8.07 MHz 1 = pilot at 2.69 MHz GNRL_RESET 0 = disable 1 = enable INITIAL_RESET 0 = disable 1 = enable FIELD NAME VALUE ADDRESS 00H 01H 02H 03H D7 D6 D5 D4 D3 D2 LOCK_INDICATOR MSE[15 to 8] MSE[7 to 0] CR_OFFSET[7 to 0] D1
TDA8960
D0
EQ_LOCK_INDICATOR
00 = mode 0 (TRLD not used) 01 = mode 1 (TRCS not used) 10 = mode 2 (TRCS and TRLD are used) 11 = mode 3 (TRLD not used; negative dF/dV
reserved Notes
3 to 0
1. Operating modes and control parameters are reset to their initial values. 2. Operating modes and control parameters are not affected.
1999 Jun 14
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Philips Semiconductors
Preliminary specification
ATSC 8-VSB demodulator and decoder
Table 14 I2C-bus diagnostic registers (read) ADDRESS 00H FUNCTION operation reserved sync recovery lock indicator equalizer lock indicator reserved 01H 02H 03H carrier recovery carrier recovery offset equalizer COMMENTS 2 1 0 MSE MSE CR_OFFSET 7 to 0 7 to 0 BIT 7 to 3 LOCK_INDICATOR
TDA8960
FIELD NAME
EQ_LOCK_INDICATOR
equalizer mean square error value 15 to 8
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDDD VI II IO Tj Tstg Tamb Ptot Ves PARAMETER digital supply voltage input voltage on any pin with respect to digital ground (VSSD) DC current into any input DC current out of any output junction temperature storage temperature ambient temperature total power dissipation electrostatic handling note 1 note 2 Notes 1. Human body model: C = 100 pF; R = 1.5 k; 3 zaps positive and 3 zaps negative. 2. Machine model: C = 200 pF; L = 0.5 H; R = 10 ; 3 zaps positive and 3 zaps negative. THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER thermal resistance from junction to ambient CONDITIONS in free air VALUE 55 UNIT K/W CONDITIONS MIN. 3.0 -0.5 - - 0 - -20 - -3000 -300 3.3 - - - - - +25 1.0 - - TYP. MAX. 3.6 V VDDD + 0.5 V tbf tbf 105 - +70 - +3000 +300 mA mA C C C W V V UNIT
1999 Jun 14
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Philips Semiconductors
Preliminary specification
ATSC 8-VSB demodulator and decoder
DC CHARACTERISTICS VDDD = 3.3 V; VSSD = 0 V; Tamb = 25 C; unless otherwise specified; note 1. SYMBOL Supply VDDD IDDD Inputs VIL VIH ILI Ci Output VOL VOH IOL IO(Z) CO(Z) LOW-level output voltage HIGH-level output voltage LOW-level output current - 2.4 - - - - - - - - 0.4 - 4 LOW-level input voltage HIGH-level input voltage input leakage current input capacitance - 2.0 - 8 - - - - 0.8 - 1 25 digital supply voltage digital supply current 3.0 - 3.3 300 3.6 - PARAMETER CONDITIONS MIN. TYP.
TDA8960
MAX.
UNIT
V mA
V V A pF
V V mA A pF
3-state output, pin AGCOUT high-impedance output current high-impedance output capacitance 1 100
I2C-bus, pins SDA and SCL VIL VIH VOL VOH IOL IL Ci Notes 1. All supply connections must be made to the same external power supply unit. 2. Open-drain output, determined by VDDD via an external pull-up resistor. LOW-level input voltage HIGH-level input voltage LOW-level output voltage HIGH-level output voltage LOW-level output current leakage current input capacitance note 2 VOL = 0.4 V VI = VSSD or VDDD VI = VSSD -0.5 0.7VDDD 0 - 3 - - - - - - - - - 0.3VDDD 0.4 3.3 - 10 8 V V V mA A pF VDDD + 0.5 V
1999 Jun 14
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Philips Semiconductors
Preliminary specification
ATSC 8-VSB demodulator and decoder
AC CHARACTERISTICS VDDD = 3.3 V; VSSD = 0 V; Tamb = 25 C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS - - note 1 - MIN. TYP. - - - - - - - - - - - - -
TDA8960
MAX.
UNIT
System clock (pin CLK) fclk(sys) tCLKH tCLKL tsu(A/D) th(A/D) tsu(D/A) th(D/A) tsu(D) th(D) tDATACLKL tDATACLKH tDATCLKW tDAT-VAL system clock frequency system clock HIGH time system clock LOW time 21.52 21.23 21.23 - - MHz ns ns
A/D interface (pins ADIN[9 to 0]) A/D interface set-up time A/D interface hold time 5 5 - - ns ns
DAC interface (pins TRSDO, TRCS, TRLD and TRSTB); see Fig.13 D/A interface set-up time D/A interface hold time 40 0 - - - - - - ns ns
Transport stream interface (pins DATA[7 to 0], SOP, ERROR and DATAVALID); see Fig.14 transport interface data set-up time transport interface data hold time transport interface DATACLK LOW time transport interface DATACLK HIGH time transport interface DATACLK period transport interface DATA to DATAVALID, ERROR and SOP 5 5 180 180 371.7 0 ns ns ns ns ns ns
I2C-bus (pins SDA and SCL); see Fig.10 fSCL tBUF tHD;STA SCL clock frequency bus free time between a STOP and START condition hold time (repeated) START condition; after this period the first clock pulse is generated LOW period of the SCL clock HIGH period of the SCL clock set-up time for a repeated START condition set-up time for STOP condition data hold time data set-up time pulse width of spikes which must be suppressed by the input filter rise time of both SDA and SCL signals note 2 0 1.3 0.6 - - - 400 - - kHz s s
tLOW tHIGH tSU;STA tSU;STO tHD;DAT tSU;DAT tSP tr
1.3 0.6 0.6 0.6 0 100 tbf
- - - - - - -
- - - - 0.9 - tbf 300
s s s s s ns ns ns
20 + 0.1Cb -
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Philips Semiconductors
Preliminary specification
ATSC 8-VSB demodulator and decoder
TDA8960
SYMBOL tf Cb
PARAMETER fall time of both SDA and SCL signals capacitive load for each bus line
CONDITIONS note 1
MIN. 20 + 0.1Cb - - - - - - -
TYP.
MAX. 300 400 ns pF
UNIT
JTAG interface (pins TDO, TDI, TCK, TMS and TRST); see Fig.11 td(TCK-TDO) pin TCK to TDO valid delay tsu(i)(TCK) th(i)(TCK) tsu(PO)L Notes 1. The chip clock (CLK) comes from a VXCO controlled by the external DAC. The control loop keeps the clock signal constant at a frequency twice the symbol rate. 2. Cb = total capacitance of one bus line in pF. input set-up time to TCK input hold time from TCK 2 10 2 10 - - - ns ns ns
Reset (pin RSTAN) power-on set-up time LOW 23 ns
1999 Jun 14
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SDA t BUF t LOW tr tf t HD;STA t SP
Philips Semiconductors
ATSC 8-VSB demodulator and decoder
Fig.10 I2C-bus timing diagram.
handbook, full pagewidth
24
SCL t HD;STA P S t HD;DAT t HIGH t SU;DAT t SU;STA t SU;STO Sr
MBC611
P
Preliminary specification
TDA8960
Philips Semiconductors
Preliminary specification
ATSC 8-VSB demodulator and decoder
TDA8960
handbook, full pagewidth
TCK td(TCK-TDO) TDO tsu(i)(TCK) valid
MGR609
th(i)(TCK)
Fig.11 JTAG I/O timing.
handbook, full pagewidth
Tcy(CLK) CLK tsu(ADIN) th(ADIN) ADIN9 to ADIN0 valid
MGR610
Tcy(clk) = 46.47 ns.
Fig.12 Input timing.
handbook, full pagewidth
TRSTB tsu(D/A) th(D/A) TRSDO valid
MGR611
Fig.13 Serial D/A converter interface I/O timing.
1999 Jun 14
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Philips Semiconductors
Preliminary specification
ATSC 8-VSB demodulator and decoder
TDA8960
handbook, full pagewidth
tDATCLKW tDATACLKH tDATACLKL DATACLK tsu(D) DATA7 to DATA0 th(D) valid tDAT-VAL ERROR VALID SOP valid
MGR612
Fig.14 Transport interface timing.
1999 Jun 14
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Philips Semiconductors
Preliminary specification
ATSC 8-VSB demodulator and decoder
APPLICATION INFORMATION
TDA8960
handbook, full pagewidth
AGC
terrestial/cable UHF/VHF
TUNER
LOW IF
A/D CONVERTER 21.52 MHz
TDA8960
MPEG transport stream
VCXO I2C-bus
D/A CONVERTER
I2C-BUS CONTROLLER
MGR597
Fig.15 Front-end unit for reception of 8-VSB signals.
1999 Jun 14
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Philips Semiconductors
Preliminary specification
ATSC 8-VSB demodulator and decoder
PACKAGE OUTLINE QFP64: plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm
TDA8960
SOT319-2
c
y X
51 52
33 32 ZE
A
e E HE A A2 A1 (A 3) Lp bp 64 1 wM D HD ZD B vM B 19 vMA 20 detail X L
pin 1 index
wM
e
bp
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 3.20 A1 0.25 0.05 A2 2.90 2.65 A3 0.25 bp 0.50 0.35 c 0.25 0.14 D (1) 20.1 19.9 E (1) 14.1 13.9 e 1 HD 24.2 23.6 HE 18.2 17.6 L 1.95 Lp 1.0 0.6 v 0.2 w 0.2 y 0.1 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 7 0o
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT319-2 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-02-04 97-08-01
1999 Jun 14
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Philips Semiconductors
Preliminary specification
ATSC 8-VSB demodulator and decoder
SOLDERING Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 230 C. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results:
TDA8960
* Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
1999 Jun 14
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Philips Semiconductors
Preliminary specification
ATSC 8-VSB demodulator and decoder
Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE WAVE BGA, SQFP PLCC(3), SO, SOJ not suitable suitable(2) suitable not recommended(3)(4) not recommended(5) suitable suitable suitable suitable suitable HLQFP, HSQFP, HSOP, HTSSOP, SMS not LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes
TDA8960
REFLOW(1)
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
1999 Jun 14
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Philips Semiconductors
Preliminary specification
ATSC 8-VSB demodulator and decoder
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
TDA8960
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
1999 Jun 14
31
Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1999
Internet: http://www.semiconductors.philips.com
SCA 66
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
545004/01/pp32
Date of release: 1999 Jun 14
Document order number:
9397 750 04248

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